Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a wafer level test of a semiconductor memory device.
Generally, a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) device supports diverse test items, and diverse tests are performed at a wafer level and a package level to reduce production costs of a semiconductor memory device and to increase a production yield thereof.
Among the tests performed at the wafer level and the package level is a multi-bit parallel test, which is simply referred to as a parallel test hereafter, for shortening test time.
The background of the parallel test is described as follows. In a semiconductor memory device, it is important to test thousands of memory cells at a high speed as well with a high reliability. Particularly, whether to shorten the development period and the test time of a semiconductor memory device directly affect the manufacturing costs of the products. Thus, reducing the test time is significant in the production efficiency and the competition between manufacturers. The conventional semiconductor memory device performs a test for each memory cell to determine whether the memory cell is normal or abnormal at the wafer level and the package level. However, as a semiconductor memory device is highly integrated, the test time increases in proportion to the high integration degree. Therefore, a parallel test is suggested to reduce the test time. The operation process of a parallel test is described as follows.
To briefly describe the operation of parallel test, the same data are written in a plurality of cells and an exclusive OR gate is used to read the written data. When the same data are read from the plurality of the cells, the semiconductor memory device is determined to be normal by outputting ‘1’, and when a different data is read from any one among the plurality of the cells, the semiconductor memory device is determined to have a fault by outputting ‘0’. The parallel test is not performed for each memory cell but performed by simultaneously activating many banks and performing write and read operations, which leads to a reduced test time.
While the parallel test performed at the package level is performed on the basis of each bank, the parallel test performed at the wafer level is performed with respect to all banks at once. This is because a series of operations for selecting a bank is performed for the parallel test performed at the package level but the series of operation for selecting a bank is not performed for the parallel test performed at the wafer level. To have a closer look at the parallel test performed at the wafer level, a probe test device may assign a channel to a certain bank address, e.g. an address <0:1> and other bank addresses, e.g. an address <2> may not be assigned with any channel. Here, the bank address <0:1> is used for another test item and the assigned channel is not used for the parallel test. The bank address <2> is not used for any other test item, and a channel is not assigned to it. Since the number of channels assigned to the probe test device is limited for the parallel test performed at the wafer level, more and more chips (or dies) may be tested simultaneously as the number of channels assigned to each chip (or die) is reduced. After all, the number of channels for testing each chip is minimized to reduce the test time. Here, the pads that are not assigned to a channel, such as the pad for the bank address <2>, are collectively coupled to a predetermined power supply voltage terminal which is provided by the probe test device.
The conventional parallel test, however, has the following features.
According to the conventional technology, a potential fault factor may be detected in each bank only when the parallel test is performed at the package level. Therefore, a countermeasure against the fault factor may be taken only in the semiconductor memory device of the package level. However, since it is difficult to cope with the fault factor at the package level state due to its characteristics, it takes more production time and cost to cope with the detected fault factor at the package level than at the wafer level.
Meanwhile, if a channel for applying the bank address <2> is assigned during the parallel test performed at the wafer level, the number of chips (or dies) to be tested at once is reduced by the limited number of channels. For example, when the probe test device includes 100 channels and four channels are assigned to each chip, 25 chips may be tested in parallel all at once. However, when the probe test device includes 100 channels and five channels including a channel for applying the bank address <2> are assigned to each chip, 20 chips may be tested in parallel all at once. Therefore, the number of chips to be tested at once is decreased and, after all, the entire test time is increased in the testing of all chips included in a wafer.